library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity RAM is
    port(
         clk: in std_logic;
         a_write: in integer range 103040 downto 0;
			a_read: in integer range 103040 downto 0;
			input: in std_logic;
	 		output: out std_logic
   	);
end RAM;

architecture Memoria of RAM is

TYPE bram IS ARRAY (103040 downto 0) OF std_logic;
signal MEM: bram;

begin
    process(clk)
    begin
       if rising_edge(clk) then
			   MEM(conv_integer(a_write))<=input;
				output <= MEM(conv_integer(a_read));
		end if;    
	 end process;
end Memoria;    
        